Syllabus

COURSE OUTLINE

Credits: 2       Hours: 3 lecture/laboratory/other

Catalog description:

Continuation of CET 4705. Further design of subsystems requiring solution by differential equations. Worst-case designs and component tolerances, development of control systems. A term project may be assigned.

 Prerequisites: CET 4705       Corequisites: none

 Instructor:      Prof. Ohbong Kwon (Email: okwon@citytech.cuny.edu)

Office hour: 10:00am-12:00pm on Tuesday @V619

                                             2:00pm-3:00pm on Wednesday and Friday @V619

 Required texts/other materials:

Textbook:

Digital Electronics with VHDL (Quartus II Version), Kleitz, William, Prentice Hall, 2005, ISBN:0131714902

Reference Books:

  1. Rapid Prototyping of Digital Systems Quartus II Edition, Springer 2006 Hamblen, James O., Hall, Tyson S., Furman, Michael D. ISBN: 978-0-387-27728-8
  2. Digital Systems Design Using VHDL , (second Edition), Charles H. Roth, Jr. and Lizy Kurian John, Thomson Publishing, 2008

Other Resources:

  • Lecture Notes and Handouts posted on CUNY Blackboard
  • Quick Start Guide Quartus II Software , Altera Corporation, http://www.altera.com/literature/manual/mnl_qts_quick_start.pdf, 2006
  • DE2 Development and Educational User Board Users Manual,

Course Outcome:

The course provides an exciting and challenging laboratory component for implementation and testing of complex engineering projects. Each digital component and system design will come with integrated laboratory experimental activities. The prototyping of complex digital logic and software systems are used as a means to demonstrate engineering practice and design. The course will introduce the students to basic design methodology, VHDL and CAD tools used in the design, synthesis and analysis of digital computer and communication systems, and Field-programmable gate array device (FPGAs). Upon successful completion of this course, the student will be able to use of the IEEE standard hardware description language (VHDL) and schematic design as practical means to implement hybrid sequential and combinational designs. Students will gain practical experience in the protocol, design, simulation and testing of digital systems. The Altera DE2 education board will provide the desired platform.

Topics Covered and Time Table:

  1. Introduction to the Altera Quartus II Design Software and Simulation (schematic capture design and VHDL design) Р week 1
  2. Programmable Logic Devices: SPLD, CPLDs and FPGAs. Getting Started with DE2 Board ‚Äď week 2
  3. Explore Switches and Lights on DE2 and VHDL. Programming FPGA board ‚Äď week 3
  4. Design Code Character and Decoder. Programming FPGA board ‚Äď week 4-5
  5. Using BDF/VHDL Components in Digital Logic Design – Multi-bit Multiplexer and Programming a FPGA.doc, weeks 6
  6. Choosing an LMP model with design ‚Äď week 7
  7. Design the controlled character patterns and Programming a FPGA – week 8

Midterm project week 9

  1. Real time clock design, counter and frequency divider application (week 10-11)
  2. System design – Integrated components and subsystems. (weeks 12-13)
  3. Memory with read and write control design (week 14)
  4. Final project and final presentation (week 15)

*Notes:  

The Instructor reserves the right to modify this outline anytime.

Project Report

Your project will be assigned and chosen based on the topic the course covered. The assignments will be posted on CUNY Blackboard. The project report will be assessed in the following format:

  • The problem written in English
  • The flowchart to solve the problem
  • The design entry included (VHDL and Schematic)
  • The simulation result for designed digital component
  • The analysis for the simulation
  • The pin assignment- assigning the circuit inputs and outputs to specific pins on the FPGA
  • The configuration mode for the FPGA device
  • The test table you designed to record and verify the designed circuit on hardware
  • The conclusion

Grading Policy:

Embedded System Design projects and reports (40%)

Midterm (10%) and Final project (40%)

Attendance (10%)

Project reports  РBe graded based on the project report formative.

– No late submission will be accepted.

– All lab reports have to be submitted to the CUNY Blackboard on time.

– Any late submission will cause point deduction (50% deduction)

Grading Scale:           A=100%-93%             A-=90%-92.9%           B+=89.9%-87%

B=86.9%-83%                        B-=82.9%-80%           C+=79.9%-77%

C=76.9%-70%                        D=69.9%-60%            F=59.9% and below

 

Quiz:                           Quizzes will be given regularly.  There is NO make-up quiz.

 Examination:             There will have a mid-term examination. The examination date will be announced at later time.  There is NO make-up examination.

Final:                          Final project presentation will be given on Week 15.  There is NO make-up final project presentation.

Academic Integrity:   Students and all others who work with information, ideas, texts, images, music, inventions, and other intellectual propertyowe their audience and sources accuracy and honesty in using, crediting, and citing sources. As a community of intellectual and professional workers, the College recognizes its responsibility for providing instruction in information literacy and academic integrity, offering models of good practice, and responding vigilantly and appropriately to infractions of academic integrity. Academic dishonesty is prohibited in The City University of New York and is punishable by penalties, including failing grades, suspension, and expulsion.

Attendance:               Under CUNY mandate, attendance in EACH class is REQUIRED and attendance will be taken at each class meeting. You are allowed a maximum of 2 absences. If you exceed that number, you may receive a WU grade. Excessive lateness (more than 5 minutes) will be considered to be an absence from that class meeting. Attendance will be counted as portion of your course grade. Each extra absence will make your final grade one down.

 Classroom Policy:      I expect you to conduct yourselves as ladies and gentlemen.  I will observe and expect you to observe basic common courtesies such as manners of address, not interrupting, not talking in class, etc.  No one has any right to engage in disruptive behavior in the classroom.  If you must leave class early, please let me know at the beginning of the period.  Obviously, you may leave at any time or impending sickness or emergency.  Otherwise please do not leave the classroom until I dismiss the class.  Also, if you have a cellular phone, please turn to vibrating or silence mode. No texting, gaming, listening to music, and watching videos during class. Thanks for your cooperation.

Helpful Hints:

1) Do not get behind; stay current with reading, homework and lab assignments.

2) Do all assignments completely and on time.

3) Actively participate in class discussions.

4) Each week review the previous lecture’s notes, write down any¬†questions you have, and bring them to class.

5) Retain your graded assignments in case there are any¬†discrepancies in the instructor’s records.

6) Ask for help as soon as you need it; don’t wait until it is too late. Student tutoring support is available in the Tech Learning Center.

Email:                         If you have any questions, please feel free to email me. But you should always include course and section number in the subject line of your email (CityTech account) and your name in your message. Otherwise, I might not reply your email promptly.                       Example:   Subject: CET4805 (D486)

Course Coordinator:

Dr. Yu Wang and Dr. Ohbong Kwon

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