In the previous work for the seven-segment, the VHDL code was written into one VHD file. In this case, the next assignment was to implement the concept of components into the seven-segment program. The way that component works, is that on a separate VHD file, the behavior of the VHD file must describe its purpose. In the top VHD file, we call the component, and then send the top VHD ports to the component, and finally receive back the information. In essence, a component is a block, and in the top VHD file, we implement that block, to use. It not only makes the code much cleaner, but it creates components that may be usable for other projects to use instead of repeating the same code over and over again.

seven_segment.vhd(TOP FILE)
library IEEE; --Libraries used
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is --Ports
	port (
	CLK: in std_logic; --FPGA 100MHz Clock
	ANODE: out std_logic_vector(0 to 6); --Anodes for each seven segment (7 anodes)
	LED: out std_logic_vector(3 downto 0); --Four LED lights representing bits
	SEG: out std_logic_vector(7 downto 0) --Eight seven-segments 
	);

end main;

architecture Behavioral of main is --Behavior of seven segment after
	
	component anode_comp is --Anode Component
	Port	(counter_in : in STD_LOGIC_VECTOR(26 downto 0);
			 anode_out : out STD_LOGIC_VECTOR(0 to 6));
	end component;
	
	component led_comp is --LED Component
	Port	(counter_in: in STD_LOGIC_VECTOR(26 downto 0);
			 led_out: out STD_LOGIC_VECTOR(3 downto 0));
	end component;
	
	component prescaler_comp is --Prescaler Component
	Port	(clock : in  STD_LOGIC;
          counter_out : out  STD_LOGIC_VECTOR (26 downto 0));
	end component;
	
	signal COUNTER: std_logic_vector(26 downto 0); --Counter signal

begin
	SEG <= "11111110"; -- Activate last seven-segment
	
	prescale1: prescaler_comp --Send ports to prescaler_comp
			Port Map (CLK,COUNTER); --Send CLK into component and receive COUNTER

	anode1: anode_comp --send ports to anode_comp
			Port MAP (COUNTER,ANODE); --Send COUNTER into component and receive ANODE
			
	led1: led_comp --send ports to led_comp
			Port MAP (COUNTER,LED); --Send COUNTER into component and receive LED

end Behavioral;

prescaler_comp.vhd
library IEEE; --Libraries used
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prescaler_comp is --Ports
    Port ( clock : in  STD_LOGIC;
			  counter_out: out STD_LOGIC_VECTOR (26 downto 0));
end prescaler_comp;

architecture Behavioral of prescaler_comp is --Counter for PRESCALER and COUNT

signal counter: std_logic_vector(26 downto 0); --counter signal
signal prescaler: std_logic_vector (26 downto 0); --prescaler signal

begin
process(clock) --Process clock
begin
	if rising_edge(clock) then --If clock is on rising edge
		if prescaler < "101111101011110000100000000" then --If prescaler is less than 100M
			prescaler <= unsigned(prescaler) + 1; --Add 1 to prescaler
		else
			prescaler  '0'); --Clear prescaler
			counter <= unsigned(counter) + 1; --Add 1 to counter
		end if;
	end if;
end process;

counter_out <= counter; --Send counter information into counter_out

end Behavioral;

anode_comp.vhd
library IEEE; --Libraries used
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity anode_comp is --Ports
    Port ( counter_in : in  STD_LOGIC_VECTOR (26 downto 0);
           anode_out : out  STD_LOGIC_VECTOR (0 to 6));
end anode_comp;

architecture Behavioral of anode_comp is --Behavior of anodes

begin

with counter_in select --When counter is equal to 'bits right of when statement', send bits to anode_out
		anode_out (0 to 6) <= "0000001" when "000000000000000000000000000",
				      "1001111" when "000000000000000000000000001",
				      "0010010" when "000000000000000000000000010",
                                      "0000110" when "000000000000000000000000011",
                                      "1001100" when "000000000000000000000000100",
                                      "0100100" when "000000000000000000000000101",
                                      "0100000" when "000000000000000000000000110",
                                      "0001111" when "000000000000000000000000111",
                                      "0000000" when "000000000000000000000001000",
                                      "0000100" when "000000000000000000000001001",       
                                      "0001000" when "000000000000000000000001010",
			              "1100000" when "000000000000000000000001011",
			              "0110001" when "000000000000000000000001100",
			              "1000010" when "000000000000000000000001101",
			              "0110000" when "000000000000000000000001110",
			              "0111000" when others;
end Behavioral;

led_comp.vdh
library IEEE; --Libraries used
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led_comp is --Ports
    Port ( counter_in : in  STD_LOGIC_VECTOR (26 downto 0);
           led_out : out  STD_LOGIC_VECTOR (3 downto 0));
end led_comp;

architecture Behavioral of led_comp is --LED behavior

begin

with counter_in select --When counter is equal to 'bits right of when statement', send bits to led_out
		led_out (3 downto 0) <= "0000" when "000000000000000000000000000",
					"0001" when "000000000000000000000000001",
					"0010" when "000000000000000000000000010",
					"0011" when "000000000000000000000000011",
					"0100" when "000000000000000000000000100",
					"0101" when "000000000000000000000000101",
					"0110" when "000000000000000000000000110",
					"0111" when "000000000000000000000000111",
					"1000" when "000000000000000000000001000",
					"1001" when "000000000000000000000001001",       
					"1010" when "000000000000000000000001010",
					"1011" when "000000000000000000000001011",
					"1100" when "000000000000000000000001100",
					"1101" when "000000000000000000000001101",
					"1110" when "000000000000000000000001110",
					"1111" when others;
end Behavioral;