Getting familiar with VHDL and the FPGA was an essential part in progressing in this project. One of the first program that we designed ran successfully. This program uses a seven-segment display to display numbers ranging from 0-9. Furthermore, in displaying those values, we also wanted to control the speed of the counter. We accomplished this task by using the built in 100Mhz clock. By using the rising edge of this clock signal, we were able to increase the value of the prescaler, and we limited the prescaler to 100M in vector form. That value represents a per second value. If we wanted the counter to go twice the speed, we would make the prescaler 50M in vector form, and then run the program. The counter will then display different value every 1/2 a second.

--This program uses one seven segment display to count from 0 to 9 and then stop. Created with a reset button.
library IEEE; --Libaries used
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is --Ports and their assignments
	port (
	CLK: in std_logic; --FPGA 100MHz clock
	RESET: in std_logic; --Reset input
	ANODE: out std_logic_vector(0 to 6); --Anodes for each seven segment (7 anodes)
	SEG: out std_logic_vector(7 downto 0) --Eight seven-segments
	);

end main;

architecture Behavioral of main is --Behavior of seven segment after
	signal COUNTER: std_logic_vector(7 downto 0); --8-bit signal counter
	signal PRESCALER: std_logic_vector(26 downto 0); --27-bit prescaler
begin
	SEG <= "11111110"; --Active low seven-segment, activates last seven-segment
	process(RESET, CLK) --Process reset and clock
	begin
		if rising_edge(CLK) then --If 100Mhz clock is on the rising edge
			if (RESET = '1') then --If reset is active
			PRESCALER  '0'); --Reset prescaler
			COUNTER  '0'); --Reset counter
			else
				if PRESCALER < "101111101011110000100000000" then --if prescaler is less than 100M
				   PRESCALER <= PRESCALER + 1; --Add 1 to prescaler
				else
				   PRESCALER  '0'); --Reset prescaler
				   COUNTER <= COUNTER + 1; --Add 1 to counter
				end if; 
			end if;
		end if;
	end process;

	with COUNTER select --When counter is equal to the vector on the right side of the 'when statement', send bits to anode 
		ANODE (0 to 6) <= "0000001" when "00000000",
                        "1001111" when "00000001",
                        "0010010" when "00000010",
                        "0000110" when "00000011",
                        "1001100" when "00000100",
                        "0100100" when "00000101",
                        "0100000" when "00000110",
                        "0001111" when "00000111",
                        "0000000" when "00001000",
                        "0000100" when "00001001",       
                        "0111000" when others;



end Behavioral;